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Ordering number : EN*A0965
LC877696B,LC877680B LC877664B,LC877648B
Overview
CMOS IC Internal 96K/80K/64K/48K-byte ROM 4096-byte RAM
8-bit 1-chip Microcontroller
The LC877600B series are an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 96K-48Kbyte ROM, 4K-byte RAM, an LCD controller/driver, a sophisticated 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer (may be divided into 8-bit timers or 8-bit PWMs), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, a day and time counter, a synchronous SIO interface (with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO interface, a UART interface (full duplex), a 12-bit 12-channel AD converter, two 12-bit PWM channels, a high-speed clock counter, a system clock frequency divider, a small signal detector, an infrared remote controller receiver function, and a 23-source 10-vector interrupt feature.
Features
ROM * 98304 x 8bits (LC877696B) * 81920 x 8bits (LC877680B) * 65536 x 8bits (LC877664B) * 49152 x 8bits (LC877648B) RAM * 4096 x 9 bits Minimum Bus Cycle Time * 83.3ns (12MHz) VDD=3.0 to 5.5V (target value) * 125ns (8MHz) VDD=2.5 to 5.5V (target value) * 250ns (4MHz) VDD=2.2 to 5.5V (target value) * 30.5s (32.768kHz) VDD=1.7 to 5.5V (target value) Note: The bus cycle time here refers to the ROM read speed.
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
Ver.0.010
61808HKIM No.A0965-1/25
LC877696B/80B/64B/48B
Minimum Instruction Cycle Time (tCYC) * 250ns (12MHz) VDD=3.0 to 5.5V (target value) * 375ns (8MHz) VDD=2.5 to 5.5V (target value) * 750ns (4MHz) VDD=2.2 to 5.5V (target value) * 91.5s(32.768kHz) VDD=1.7 to 5.5V (target value) Ports * Normal withstand voltage I/O ports Ports whose I/O direction can be designated in 1-bit units Ports whose I/O direction can be designated in 4-bit units * Normal withstand voltage input port * LCD ports Segment output Common output Bias terminals for LCD driver Other functions Input/output ports Input ports * Dedicated oscillator ports * Reset pins * Power pins
23 (P1n, P30 to P31, P70 to P73, P8n, XT2) 8 (P0n) 1 (XT1) 32 (S00 to S31) 4 (COM0 to COM3) 3 (V1 to V3) 32 (PAn, PBn, PCn, PDn,) 7 (PLn) 2 (CF1, CF2) 1 (RES) 6 (VSS1 to VSS3, VDD1 to VDD3)
LCD Controller 1) Seven display modes are available (static, 1/2, 1/3, 1/4 duty x 1/2, 1/3 bias) 2) Segment output and common output can be switched to general-purpose input/output ports Small Signal Detection (MIC signals etc) 1) Counts pulses with the level which is greater than a preset value 2) 2-bit counter Timers * Timer 0: 16-bit timer/counter with capture registers. Mode 0: 8-bit timer with an 8-bit programmable prescaler (with 8-bit capture registers) x 2 channels Mode 1: 8-bit timer with an 8-bit programmable prescaler (with 8-bit capture registers) + 8-bit counter (with 8-bit capture registers) Mode 2: 16-bit timer with an 8-bit programmable prescaler (with 16-bit capture registers) Mode 3: 16-bit counter (with 16-bit capture registers) * Timer 1: 16-bit timer that supports PWM/toggle outputs Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer with an 8-bit prescaler (with toggle outputs) Mode 1: 8-bit PWM with an 8-bit prescaler x 2 channels Mode 2: 16-bit timer with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.) * Timer 4: 8-bit timer with a 6-bit prescaler * Timer 5: 8-bit timer with a 6-bit prescaler * Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) * Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) * Base timer 1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler output. 2) Interrupts programmable in 5 different time schemes * Day and time counter 1) Used with a base timer, the day and time counter can be used as a 65000 day + minute + second counter.
No.A0965-2/25
LC877696B/80B/64B/48B
High-speed Clock Counter 1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz). 2) Can generate output real-time. SIO * SIO0: 8-bit synchronous serial interface 1) LSB first/MSB first mode selectable 2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC) 3) Automatic continuous data transmission (1 to 256 bits specifiable in 1-bit units, suspension and resumption of data transmission possible in 1-byte units) * SIO1: 8-bit asynchronous/synchronous serial interface Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks) Mode 1: Asynchronous serial I/O (half-duplex, 8-data bits, 1-stop bit, 8 to 2048 tCYC baudrates) Mode 2: Bus mode 1 (start bit, 8-data bits, 2 to 512 tCYC transfer clocks) Mode 3: Bus mode 2 (start detect, 8-data bits, stop detect) UART * Full duplex * 7/8/9 bit data bits selectable * 1 stop bit (2-bit in continuous data transmission) * Built-in baudrate generator AD Converter: 12 bits x 12 channels PWM: Multi frequency 12-bit PWM x 2 channels Infrared Remote Control Receiver Circuit 1) Noise reduction function (Time constant of noise reduction filter: approx. 120s, when selecting a 32.768kHz crystal oscillator as a reference clock.) 2) X'tal HOLD mode cancellation function Watchdog Timer * External RC watchdog timer * Interrupt and reset signals selectable Clock Output Function 1) Can output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32,or 1/64 as system clock. 2) Can output the source oscillation clock for the sub clock.
No.A0965-3/25
LC877696B/80B/64B/48B
Interrupts Source Flags * 23 sources, 10 vector addresses 1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector address takes precedence.
No. 1 2 3 4 5 6 7 8 9 10 Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level X or L X or L H or L H or L H or L H or L H or L H or L H or L H or L INT0 INT1 INT2/T0L/remote control receiver INT3/base timer 0/base timer 1 T0H T1L/T1H SIO0/UART1 receive SIO1/UART1 transmit ADC/MIC/T6/T7/PWM4, PWM5 Port 0/T4/T5 Interrupt Source
* Priority levels X > H > L * Of interrupts of the same level, the one with the smallest vector address takes precedence. * IFLG (List of interrupt source flag function) 1) Shows a list of interrupt source flags that caused a branching to a particular vector address Subroutine Stack Levels: 2048 levels maximum (The stack is allocated in RAM.) High-speed Multiplication/Division Instructions * 16 bits x 8 bits (5 tCYC execution time) * 24 bits x 16 bits (12 tCYC execution time) * 16 bits / 8 bits (8 tCYC execution time) * 24 bits / 16 bits (12 tCYC execution time) Oscillation Circuits * RC oscillation circuit (internal): For system clock * CF oscillation circuit: For system clock, with internal Rf and external Rd * Crystal oscillation circuit: For low-speed system clock, with internal Rf and external Rd * Multifrequency RC oscillation circuit (internal): For system clock 1) Adjustable in 4% (typ) increments from the selected center frequency. 2) Measures the frequency of the source oscillation clock using the input signal from XT1 as the reference. System Clock Divider Function * Can run on low current. * The minimum instruction cycle selectable from 300ns, 600ns, 1.2s, 2.4s, 4.8s, 9.6s, 19.2s, 38.4s, and 76.8s (at a main clock rate of 10MHz). System Clock Multiplier Function * Allows the 2 or 3 times the clock frequency to be selected when the crystal oscillation output is used as the system clock.
No.A0965-4/25
LC877696B/80B/64B/48B
Standby Function * HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation. (Some parts of the serial transfer function stops operation.) 1) Oscillation is not stopped automatically. 2) Canceled by a system reset or occurrence of an interrupt * HOLD mode: Suspends instruction execution and the operation of the peripheral circuits. 1) The CF, RC, X'tal, and multifrequency RC oscillators automatically stop operation. 2) There are three ways of resetting the HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, and INT2, pins to the specified level (3) Having an interrupt source established at port 0 * X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer and infrared remote controller circuit. 1) The CF, RC, and multifrequency RC oscillators automatically stop operation 2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained. 3) There are five ways of resetting the X'tal HOLD mode. (1) Setting the reset pin to the low level (2) Setting at least one of the INT0, INT1, and INT2 pins to the specified level (3) Having an interrupt source established at port 0 (4) Having an interrupt source established in the base timer circuit (5) Having an interrupt source established in the infrared remote control receiver circuit On-chip Debugger function * Supports software debugging with the IC mounted on the target board. Package Form * QFP80(14x14): * TQFP80J(12x12):
Lead-free type Lead-free type
Development Tools * On-chip debugger: TCB87-TypeB + LC87F76C8A Flash ROM Programming Board
Package QFP80(14x14) TQFP80J(12x12) Programming Board W87F71256QF W87F71256SQ
Same Package and Pin Assignment as Flash ROM Version 1) LC877600 series options can be specified by using flash ROM data. Thus the board used for mass production can be used for debugging and evaluation without modifications. 2) If the program for the mask ROM version is used, the size of the available ROM/RAM spaces is the same as that of the mask ROM version.
No.A0965-5/25
LC877696B/80B/64B/48B
Package Dimensions
unit : mm (typ) 3255
17.2 60 61 41 40
80 1 (0.83) 0.65 0.25 20
21 0.15
3.0max
0.1
(2.7)
SANYO : QFP80(14X14)
Package Dimensions
unit : mm (typ) 3290
14.0 12.0 60 61 41 40
14.0 17.2
0.8
12.0
21
14.0
80 1 0.5 (1.25) 0.2 20
14.0
0.125
1.2max
0.1
(1.0)
SANYO : TQFP80J(12X12)
0.5
No.A0965-6/25
LC877696B/80B/64B/48B
Pin Assignment
P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ RES XT1/AN10 XT2/AN11 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/MICIN/AN7 P70/INT0/T0LCP/AN8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
COM0/PL0 COM1/PL1 COM2/PL2 COM3/PL3 P30/ PWM4 VSS3 VDD3 P31/ PWM5 P00/UTX1 P01/URX1 P02 P03 P04 P05/CKO P06/T6O P07/T7O P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
V1/PL4 V2/PL5 V3/PL6 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 S23/PC7 S22/PC6 S21/PC5 S20/PC4 S19/PC3 S18/PC2 S17/PC1 S16/PC0 S15/PB7
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
LC877696B LC877680B LC877664B LC877648B
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VSS2 VDD2 S14/PB6 S13/PB5 S12/PB4 S11/PB3 S10/PB2 S9/PB1 S8/PB0 S7/PA7 S6/PA6 S5/PA5 S4/PA4 S3/PA3 S2/PA2 S1/PA1 S0/PA0 P73/INT3/T0IN/RMIN P72/INT2/T0IN/NKIN P71/INT1/T0HCP/AN9
Top view
SANYO: QFP80(14x14) "Lead-free Type" SANYO: TQFP80J(12x12) "Lead-free Type"
No.A0965-7/25
LC877696B/80B/64B/48B
System Block Diagram
Interrupt control
IR
PLA
Standby control
Flash ROM
CF RC VMRC X'tal Clock generator
PC
SIO0
Bus interface
ACC
SIO1
Port 0
B register
Timer 0 (High speed clock counter)
Port 1
C register
Timer 1
Port 3 ALU
Timer 4
Port 7
Timer 5
Port 8
PSW
Timer 6
INT0 to INT3 Noise rejection filter
RAR
Timer 7
Small signal detector
RAM
LCD controller
ADC
Stack pointer
UART1
Infrared remote control receiver
Watchdog timer
Base timer
Day and time counter
PWM4/PWM5
No.A0965-8/25
LC877696B/80B/64B/48B
Pin Description
Pin Name VSS1 VSS2 VSS3 VDD1 VDD2 VDD3 PORT0 P00 to P07 I/O * 8-bit I/O port * I/O specifiable in 4-bit units * Pull-up resistors can be turned on and off in 4-bit units. * Input for HOLD release * Input for port 0 interrupt * Shared pins P00: UART1 transmit P01: UART1 receive P05: Clock output (system clock/subclock selectable) P06: Timer 6 toggle output P07: Timer 7 toggle output PORT1 P10 to P17 I/O * 8-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units. * Shared pins P10: SIO0 data output P11: SIO0 data input/bus I/O P12: SIO0 clock I/O P13: SIO1 data output P14: SIO1 data input/bus I/O P15: SIO1 clock I/O P16: Timer 1 PWML output P17: Timer 1PWMH output/beeper output PORT3 P30 to P31 I/O * 2-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units. * Shared pins P30: PWM4 output P31: PWM5 output PORT7 P70 to P73 I/O * 4-bit I/O port * I/O specifiable in 1-bit units * Pull-up resistors can be turned on and off in 1-bit units. * Shared pins P70: INT0 input/HOLD release input/timer 0L capture input/watchdog timer output P71: INT1 input/HOLD release input/timer 0H capture input P72: INT2 input/HOLD release input/timer 0 event input/timer 0L capture input/ high speed clock counter input P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input/ infrared remote control receiver input AD converter input ports: AN8 (P70), AN9 (P71) * Interrupt acknowledge type Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising & Falling disable disable enable enable H level enable enable disable disable L level enable enable disable disable No Yes Yes Yes I/O - power supply pin Description Option No
-
+ power supply pin
No
Continued on next page.
No.A0965-9/25
LC877696B/80B/64B/48B
Continued from preceding page.
Pin Name PORT8 P80 to P87 I/O I/O * 8-bit I/O port * I/O specifiable in 1-bit units * Shared pins AD converter input ports: AN0 to AN7 Small signal detector input port: MICIN (P87) S0/PA0 to S7/PA7 S8/PB0 to S15/PB7 S16/PC0 to S23/PC7 S24/PD0 to S31/PD7 COM0/PL0 to COM3/PL3 V1/PL4 to V3/PL6 RES XT1 Input Input I/O I/O I/O I/O I/O I/O * Segment output for LCD * Can be used as general-purpose I/O port (PA) * Segment output for LCD * Can be used as general-purpose I/O port (PB) * Segment output for LCD * Can be used as general-purpose I/O port (PC) * Segment output for LCD * Can be used as general-purpose I/O port (PD) * Common output for LCD * Can be used as general-purpose input port (PL) * LCD drive bias power supply * Can be used as general-purpose input port (PL) * Shared pins Reset pin * 32.768kHz crystal oscillator input pin * Shared pins General-purpose input port Must be connected to VDD1 if not to be used. AD converter input port: AN10 XT2 I/O * 32.768kHz crystal oscillator output pin * Shared pins General-purpose I/O port Must be set for oscillation and kept open if not to be used. AD converter input port: AN11 CF1 CF2 Input Output Ceramic resonator input pin Ceramic resonator output pin No No No No No No No No No No No Description Option No
No.A0965-10/25
LC877696B/80B/64B/48B
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor. Data can be read into any input port even if it is in the output mode.
Port Name P00 to P07 Option Selected in Units of 1 bit Option Type 1 2 P10 to P17 1 bit 1 2 P30 to P31 1 bit 1 2 P70 P71 to P73 P80 to P87 S0/PA0 to S31/PD7 COM0/PL0 to COM3/PL3 V1/PL4 to V3/PL6 XT1 XT2 No No No No No No No No CMOS N-channel open drain CMOS N-channel open drain CMOS N-channel open drain N-channel open drain CMOS N-channel open drain CMOS Input only Input only Input only Output for 32.768kHz crystal oscillator (Nch-open drain when in general-purpose output mode) Output Type Pull-up Resistor Programmable (Note) No Programmable Programmable Programmable Programmable Programmable Programmable No Programmable No No No No
Note: Programmable pull-up resistors for port 0 are controlled in 4 bit units (P00 to 03, P04 to 07). *1 Connect the IC as shown below to minimize the noise input to the VDD1 pin. Be sure to electrically short the VSS1, VSS2, and VSS3 pins.
LSI VDD1 Power supply
For backup *2
VDD2 VDD3
VSS1
VSS2 VSS3
*2 The internal memory is sustained by VDD1. If none of VDD2 and VDD3 are backed up, the high level output at the ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus shortening the backup time. Make sure that the port outputs are held at the low level in the HOLD backup mode.
No.A0965-11/25
LC877696B/80B/64B/48B
Absolute Maximum Ratings at Ta = 25C, VSS1 = VSS2 = VSS3 = 0V
Parameter Maximum supply voltage Supply voltage for LCD Input voltage Input/output voltage Peak output current IOPH(2) IOPH(3) IOPH(4) Average output current (Note 1-1) High level output current IOMH(2) IOMH(3) IOMH(4) Total output current IOAH(2) IOAH(3) IOAH(4) IOAH(5) IOAH(6) IOAH(7) Peak output current Low level output current IOPL(1) IOPL(2) IOPL(3) IOPL(4) Average output current (Note 1-1) IOML(1) IOML(2) IOML(3) IOML(4) Port 30 Ports 0, 1, 3 Ports 71 to 73 Ports A, B Ports C, D Ports A, B, C, D Ports 0, 1 Port 3 * Ports 7, 8 * XT2 Ports A, B, C, D Ports 0, 1 Port 3 * Ports 7, 8 * XT2 Ports A, B, C, D Per applicable pin Per applicable pin Per applicable pin Per applicable pin Per applicable pin IOAH(1) Port 3 Ports 71 to 73 Ports A, B, C, D Ports 0, 1, 31 IOMH(1) Port 3 Ports 71 to 73 Ports A, B, C, D Ports 0, 1 IOPH(1) VI(1) VIO(1) VLCD V1/PL4, V2/PL5, V3/PL6 * Port L * XT1, CF1, RES * Ports 0, 1, 3, 7, 8 * Ports A, B, C, D * XT2 Ports 0, 1 * CMOS output selected * Per applicable pin * CMOS output selected * Per applicable pin Per applicable pin Per applicable pin * CMOS output selected * Per applicable pin * CMOS output selected * Per applicable pin Per applicable pin Per applicable pin Total of currents at all applicable pins Total of currents at all applicable pins Total of currents at all applicable pins Total of currents at all applicable pins Total of currents at all applicable pins Total of currents at all applicable pins Total of currents at all applicable pins Per applicable pin Per applicable pin Per applicable pin -10 -20 -5 -5 -7.5 -15 -3 -3 -25 -15 -40 mA -5 -25 -25 -45 20 30 10 10 15 20 7.5 7.5 -0.3 VDD+0.3 VDD1=VDD2=VDD3 Symbol VDD max Pin/Remarks VDD1,VDD2, VDD3 Conditions VDD[V] VDD1=VDD2=VDD3 min -0.3 -0.3 -0.3 Specification typ max +6.5 VDD VDD+0.3 V unit
Note 1-1: Average output current refers to the average of output currents measured for a period of 100ms.
Continued on next page.
No.A0965-12/25
LC877696B/80B/64B/48B
Continued from preceding page.
Parameter Total output current IOAL(2) Low level output current IOAL(3) IOAL(4) IOAL(5) IOAL(6) IOAL(7) Maximum power dissipation Operating ambient temperature Storage ambient temperature Tstg Topr Pd max Port 30 Ports 0, 1, 3 * Ports 7, 8 * XT2 Ports A, B Ports C, D Ports A, B, C, D QFP80(14x14) TQFP80J(12x12) -40 -55 Symbol IOAL(1) Pin/Remarks Ports 0, 1, 31 Conditions VDD[V] Total of currents at all applicable pins Total of currents at all applicable pins Total of currents at all applicable pins Total of currents at all applicable pins Total of currents at all applicable pins Total of currents at all applicable pins Total of currents at all applicable pins Ta=-40 to +85C min Specification typ max 45 45 80 20 45 45 80 289.51 236.74 +85 C +125 mA unit
mW
Note 1-1: Average output current refers to the average of output currents measured for a period of 100 ms.
Allowable Operating Range at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter Operating supply voltage Symbol VDD(1) VDD(2) VDD(3) VDD(4) Memory sustaining supply voltage High level input voltage VIH(2) VIH(1) * Ports 0, 3, 8 * Ports A, B, C, D * Port L * Port 1 * Ports 71 to 73 * Port 70 port input/ interrupt side VIH(3) VIH(4) VIH(5) VIH(6) Port 71 interrupt side Port 87 small signal input side Port 70 watchdog timer side XT1, XT2, CF1, RES Output disabled * Output disabled * When INT1VTSL=1 Output disabled 1.7 to 5.5 1.7 to 5.5 1.7 to 5.5 1.7 to 5.5 0.85VDD 0.75VDD 0.9VDD 0.75VDD VDD VDD VDD VDD * Output disabled * When INT1VTSL=0 (P71only) 1.7 to 5.5 0.3VDD +0.7 VDD Output disabled 1.7 to 5.5 0.3VDD +0.7 VDD V VHD VDD1 Pin/Remarks VDD1=VDD2=VDD3 Conditions VDD[V] 0.237stCYC200s 0.356stCYC200s 0.712stCYC200s 10stCYC200s RAM and register contents sustained in HOLD mode 1.5 5.5 min 3.0 2.5 2.2 1.7 Specification typ max 5.5 5.5 5.5 5.5 unit
Continued on next page.
No.A0965-13/25
LC877696B/80B/64B/48B
Continued from preceding page.
Parameter Low level input voltage Symbol VIL(1) Pin/Remarks * Ports 0, 3, 8 * Ports A, B, C, D * Port L VIL(2) * Port 1 * Ports 71 to 73 * Port 70 port input/ interrupt side VIL(3) VIL(4) VIL(5) VIL(6) Instruction cycle time (Note 2-1) tCYC Port 71 interrupt side Port 87 small signal input side Port 70 watchdog timer side XT1, XT2, CF1, RES Output disabled * Output disabled * When INT1VTSL=1 Output disabled * Output disabled * When INT1VTSL=0 (P71 only) Conditions VDD[V] Output disabled 4.0 to 5.5 2.2 to 4.0 4.0 to 5.5 1.7 to 4.0 1.7 to 5.5 1.7 to 5.5 1.7 to 5.5 1.7 to 5.5 3.0 to 5.5 2.5 to 5.5 2.2 to 5.5 1.7 to 5.5 External system clock frequency FEXCF(1) CF1 * CF2 pin open * System clock frequency division ratio=1/1 * External system clock DUTY505% * CF2 pin open * System clock frequency division ratio=1/2 Oscillation frequency range (Note 2-2) FmCF(2) FmCF(3) FmRC FmVMRC(1) CF1, CF2 CF1, CF2 FmCF(1) CF1, CF2 * 12MHz ceramic oscillation * See figure 1. * 8MHz ceramic oscillation * See figure 1. * 4MHz ceramic oscillation * See figure 1. Internal RC oscillation * Multifrequency RC source oscillation * VMRAJ2 to 0=4, VMFAJ2 to 0=0, When VMSL4M=0 FmVMRC(2) * Multifrequency RC source oscillation * VMRAJ2 to 0=4, VMFAJ2 to 0=0, When VMSL4M=1 FsX'tal Multifrequency RC oscillation usable range Multifrequency RC oscillation adjustment range VmADJ(1) VmADJ(2) VMRAJn 1STEP (Wide range) VMFAJn 1STEP (Narrow range) 2.2 to 5.5 1 4 8 OpVMRC(1) OpVMRC(2) XT1, XT2 * 32.768kHz crystal oscillation * See figure 2. When VMSL4M=0 When VMSL4M=1 1.7 to 5.5 2.2 to 5.5 2.2 to 5.5 2.2 to 5.5 8 3.5 8 32.768 10 4 24 12 MHz 4.5 64 % kHz 2.2 to 5.5 4 2.2 to 5.5 10 3.0 to 5.5 2.5 to 5.5 2.2 to 5.5 3.0 to 5.5 2.5 to 5.5 2.2 to 5.5 2.2 to 5.5 0.3 0.2 0.2 0.2 12 8 MHz 4 1.0 2.0 24.4 16 8 2.2 to 5.5 0.1 4 3.0 to 5.5 2.5 to 5.5 min VSS VSS VSS VSS VSS VSS VSS VSS 0.237 0.356 0.712 10 0.1 0.1 Specification typ max 0.15VDD +0.4 0.2VDD 0.1VDD +0.4 0.2VDD V 0.45VDD 0.25VDD 0.8VDD -1.0 0.25VDD 200 200 200 200 12 8 s unit
Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a division ratio of 1/2. Note 2-2: See Tables 1 and 2 for the oscillation constants.
No.A0965-14/25
LC877696B/80B/64B/48B
Electrical Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter High level input current Symbol IIH(1) Pin/Remarks * Ports 0, 1, 3, 7, 8 * Ports A, B, C, D * Port L IIH(2) IIH(3) IIH(4) IIH(5) RES XT1, XT2 CF1 Port 87 small signal input side Low level input current IIL(1) * Ports 0, 1, 3, 7, 8 * Ports A, B, C, D * Port L IIL(2) IIL(3) IIL(4) IIL(5) RES XT1, XT2 Conditions VDD[V] * Output disabled * Pull-up resistor off * VIN=VDD (including output Tr's off leakage current) VIN=VDD * When configured as input ports * VIN=VDD VIN=VDD VIN=VBIS+0.5V (VBIS denotes bias voltage) * Output disabled * Pull-up resistor off * VIN=VSS (including output Tr's off leakage current) VIN=VSS * When configured as input ports * VIN=VSS CF1 Port 87 small signal input side High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) VOH(7) VOH(8) VOH(9) VOH(10) VOH(11) Low level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) VOL(9) VOL(10) LCD output voltage deviation VODLS S0 to S31 * Ports 0, 1 * Port 3 (PWM4, 5 function output mode) Port 3 (Port function output mode) * Ports 7, 8 * XT2 Ports A, B, C, D Ports A, B, C, D Ports 71 to 73 CMOS output ports 30, 31 CMOS output ports 0, 1 VIN=VSS VIN=VBIS-0.5V (VBIS denotes bias voltage) IOH=-1mA IOH=-0.4mA IOH=-0.2mA IOH=-10mA IOH=-1.6mA IOH=-1mA IOH=-0.4mA IOH=-0.2mA IOH=-1mA IOH=-0.4mA IOH=-0.2mA IOL=10mA IOL=1.6mA IOL=1mA IOL=30mA IOL=5mA IOL=2.5mA IOL=1.6mA IOL=1mA IOH=1.6mA IOL=1mA * IO=0mA * VLCD, 2/3VLCD 1/3VLCD level output * See Fig. 8. VODLC COM0 to COM3 * IO=0mA * VLCD, 2/3VLCD 1/2VLCD, 1/3VLCD level output * See Fig. 8. LCD bias resistor RLCD(1) RLCD(2) Resistance per one bias resister * Resistance per one bias resister * 1/2 resistance mode See Fig. 8. 2.2 to 5.5 30 See Fig. 8. 2.2 to 5.5 60 k 2.2 to 5.5 0 0.2 1.7 to 5.5 1.7 to 5.5 1.7 to 5.5 4.5 to 5.5 1.7 to 4.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5-5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 4.5 to 5.5 3.0 to 5.5 2.2 to 5.5 3.0 to 5.5 2.2 to 5.5 3.0 to 5.5 2.2 to 5.5 -1 -1 -15 -15 -10 VDD-1 VDD-0.4 VDD-0.4 VDD-1.5 VDD-0.4 VDD-0.4 VDD-0.4 VDD-0.4 VDD-1 VDD-0.4 VDD-0.4 1.5 0.4 0.4 1.5 0.4 0.4 0.4 0.4 0.4 0.4 V -8.5 -5.5 -4.2 -1.5 1.7 to 5.5 -1 1.7 to 5.5 1.7 to 5.5 1.7 to 5.5 4.5 to 5.5 1.7 to 4.5 4.2 1.5 8.5 5.5 1 1 15 15 10 A 1.7 to 5.5 1 min Specification typ max unit
2.2 to 5.5
0
0.2
Continued on next page. No.A0965-15/25
LC877696B/80B/64B/48B
Continued from preceding page.
Parameter Pull-up MOS Tr. resistance Hysteresis voltage Symbol Rpu(1) Rpu(2) VHYS(1) VHYS(2) Pin capacitance CP Pin/Remarks * Ports 0, 1, 3, 7 * Ports A, B, C, D * Ports 1, 7 * RES Port 87 small signal input side All pins * VIN=VSS for pins other than that under test * f=1MHz * Ta=25C Input sensitivity Vsen Port 87 small signal input side 2.2 to 5.5 0.12VDD Vp-p 1.7 to 5.5 10 pF Conditions VDD[V] VOH=0.9VDD 4.5 to 5.5 2.2 to 4.5 2.2 to 5.5 2.2 to 5.5 min 15 18 Specification typ 35 50 0.1VDD V 0.1VDD max 80 150 unit k
Serial I/O Characteristics at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Parameter Frequency Low level Input clock pulse width High level pulse width tSCKHA(1) * Continuous data transmission/reception mode Serial clock * See Fig. 6. * (Note 4-1-2) Frequency Low level Output clock pulse width High level pulse width tSCKHA(2) * Continuous data transmission/reception mode * CMOS output selected * See Fig. 6. Data setup time Serial input tsDI(1) SB0(P11), SI0(P11) Data hold time thDI(1) * Must be specified with respect to rising edge of SIOCLK * See Fig. 6. 2.2 to 5.5 0.03 Output delay Input clock time tdDO(2) tdDO(1) SO0(P10), SB0(P11) * Continuous data transmission/reception mode * (Note 4-1-3) * Synchronous 8-bit mode * (Note 4-1-3) 2.2 to 5.5 Output clock tdDO(3) (Note 4-1-3) (1/3)tCYC +0.05 0.03 tSCKH(2) +2tCYC tSCKH(2) 2.2 to 5.5 tSCK(2) tSCKL(2) SCK0(P12) * CMOS output selected * See Fig. 6. 4/3 1/2 tSCK 1/2 tSCKH(2) +(10/3) tCYC tCYC 4 tSCKH(1) 2.2 to 5.5 Symbol tSCK(1) tSCKL(1) Pin/Remarks SCK0(P12) Conditions VDD[V] See Fig. 6. min 2 1 1 tCYC Specification typ max unit
(1/3)tCYC +0.05 1tCYC +0.05 s
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use. Note 4-1-2: To use serial-clock-input in continuous transmission/reception mode, a time from SI0RUN being set when serial clock is "H" to the first falling edge of the serial clock must be longer than tSCKHA. Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of output state change in open drain output mode. See Fig. 6.
Serial output
No.A0965-16/25
LC877696B/80B/64B/48B
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Parameter Frequency Input clock Low level pulse width High level pulse width Frequency Output clock Low level pulse width High level pulse width Data setup time Serial input tsDI(2) SB1(P14), SI1(P14) Data hold time thDI(2) * Must be specified with respect to rising edge of SIOCLK. * See Fig. 6. 2.2 to 5.5 0.03 Output delay Serial output time tdDO(4) SO1(P13), SB1(P14) * Must be specified with respect to falling edge of SIOCLK. * Must be specified as the time to the beginning of output state change in open drain output mode. * See Fig. 6. 2.2 to 5.5 (1/3)tCYC +0.05 s 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) * CMOS output selected * See Fig. 6. 2.2 to 5.5 tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/Remarks SCK1(P15) See Fig.6. Conditions VDD[V] min 2 2.2 to 5.5 1 tCYC 1 2 1/2 tSCK 1/2 Specification typ max unit
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Pulse Input Conditions at Ta = -40C to +85C, VSS1 = VSS2 = VSS3 = 0V
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIH(5) tPIL(5) tPIH(6) tPIL(6) tPIL(7) RES RMIN(P73) Pin/Remarks INT0(P70), INT1(P71), INT2(P72) INT3(P73) when noise filter time constant is 1/1 INT3(P73) when noise filter time constant is 1/32 INT3(P73) when noise filter time constant is 1/128 MICIN(P87) Conditions VDD[V] * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. * Interrupt source flag can be set. * Event inputs for timer 0 are enabled. The pulses can be counted by the small signal sensor/counter. The pulses can be recognized as signals by the infrared remote control receiver circuit. Resetting is enabled. 1.7 to 5.5 2000 2.2 to 5.5 3 1.7 to 5.5 1 RMCK (Note5-1) s 1.7 to 5.5 256 1.7 to 5.5 64 tCYC 1.7 to 5.5 2 1.7 to 5.5 1 min Specification typ max unit
Note 5-1: RMCK denotes the frequency of the base clock (1tCYC to 128tCYC/subclock source oscillation frequency) for the
infrared remote control receiver circuit
Serial clock
No.A0965-17/25
LC877696B/80B/64B/48B
AD Converter Characteristics at VSS1 = VSS2 = 0V
<12-bit AD conversion mode at Ta = -30C to +85C> (To be determined after evaluation)
Parameter Resolution Absolute accuracy Conversion time TCAD N ET Symbol Pin/Remarks AN0(P80) to AN7(P87), AN8(P70), AN9(P71), AN10(XT1) AN11(XT2) (Note 6-1) (Note 6-1) Ta=-10 to 50C See "Conversion time calculation method". (Note 6-2) See "Conversion time calculation method". (Note 6-2) Ta=-10 to 50C Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN 3.0 to 5.5 3.0 to 5.5 -1 -1 12 V A 3.0 to 5.5 1 Conditions VDD[V] 3.0 to 5.5 3.0 to 5.5 4.0 to 5.5 3.0 to 5.5 3.0 to 5.5 32 64 VSS min Specification typ 12 16 115 115 VDD s max unit bit LSB
<8-bit AD conversion mode at Ta =-30 to +85C>
Parameter Resolution Absolute accuracy Conversion time tCAD(2) N ET(1) ET(2) tCAD(1) Symbol Pin/Remarks AN0(P10) to AN7(P17), AN8(P70), AN9(Internal reference voltage) See "Conversion time calculation method". (Note 6-2) Ta=-10 to +55C See "Conversion time calculation method". (Note 6-2) See "Conversion time calculation method". (Note 6-2) Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN 3.0 to 5.5 2.0 to 5.5 2.0 to 5.5 2.0 to 5.5 -1 7.48 VSS 7.66 8.26 VDD 1 V A 2.0 to 5.5 7.48 7.66 8.26 ms Specified with tCAD(1) (Note 6-1) Specified with tCAD(2) (Note 6-1) Conditions VDD[V] 2.0 to 5.5 3.0 to 5.5 2.0 to 5.5 4.0 to 5.5 3.0 to 5.5 20 40 min Specification typ 8 1.5 4.0 90 90 s max unit bit LSB
12-bit AD conversion mode: TCAD (conversion time) = ((52/(division ratio)) + 2) x (1/3)xtCYC 8-bit AD conversion mode: TCAD (conversion time) = ((32/(division ratio)) + 2) x (1/3)xtCYC
External oscillator FmCF[MHz] 12MHz Supply Voltage Range VDD[V] 4.0 to 5.5 3.0 to 5.5 32.768kHz 2.0 to 5.5 3.0 to 5.5 System Clock Division (SYSDIV) 1/1 1/1 1/1 1/1 Cycle Time tCYC 250ns 250ns 91.5s 250s AD Frequency Division Ratio (ADDIV) 1/8 1/16 1/8 1/8 12-bit AD 34.8s 69.5s 8-bit AD 21.5s 42.8s 7.86ms 7.86ms Conversion Time (TCAD)
Note 6-1: The quantization error (1/2LSB) is excluded from the absolute accuracy value. The absolute accuracy refers to the accuracy that is measured while there is no change in the I/O state of the pins adjacent to the analog input channel. Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till the time the complete digital-conversion-value corresponding to the analog input value is loaded in the required register. The conversion time becomes twice the normal value in the following cases: * The AD conversion is carried out in the 12-bit AD conversion mode for the first time after a system reset. * The AD conversion is carried out for the first time after the AD conversion mode is switched from 8-bit to 12-bit AD conversion mode.
No.A0965-18/25
LC877696B/80B/64B/48B
Consumption Current Characteristics at Ta = -20C to +70C, VSS1 = VSS2 = VSS3 = 0V (To be determined after evaluation)
Parameter Normal mode consumption current (Note 7-1) IDDOP(2) Symbol IDDOP(1) Pin/Rema rks VDD1 =VDD2 =VDD3 Conditions VDD[V] * FmCF=12MHz ceramic oscillation mode * FmX'tal=32.768kHz crystal oscillation mode * System clock set to 12MHz side * Internal RC oscillation stopped * Multifrequency RC oscillation stopped * 1/1 frequency division ratio IDDOP(3) IDDOP(4) IDDOP(5) IDDOP(6) IDDOP(7) IDDOP(8) IDDOP(9) IDDOP(10) IDDOP(11) IDDOP(12) * FmCF=8MHz ceramic oscillation mode * FmX'tal=32.768kHz crystal oscillation mode * System clock set to 8MHz side * Internal RC oscillation stopped * Multifrequency RC oscillation stopped * 1/1 frequency division ratio * FmCF=4MHz ceramic oscillation mode * FmX'tal=32.768kHz crystal oscillation mode * System clock set to 4MHz side * Internal RC oscillation stopped * Multifrequency RC oscillation stopped * 1/2 frequency division ratio * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz crystal oscillation mode * System clock set to internal RC oscillation * Multifrequency RC oscillation stopped * 1/2 frequency division ratio * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz crystal oscillation mode * Internal RC oscillation stopped IDDOP(13) * System clock set to 10MHz multifrequency RC oscillation * 1/1 frequency division ratio IDDOP(14) IDDOP(15) IDDOP(16) IDDOP(17) * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz crystal oscillation mode * Internal RC oscillation stopped * System clock set to 4MHz multifrequency RC oscillation * 1/1 frequency division ratio * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz crystal oscillation mode IDDOP(18) IDDOP(19) * System clock set to 32.768kHz side * Internal RC oscillation stopped * Multifrequency RC oscillation stopped * 1/2 frequency division ratio 1.7 to 3.0 6.9 63.8 3.0 to 3.6 9.2 74.2 2.2 to 3.0 4.5 to 5.5 1.1 27.6 4.1 126.3 A 4.5 to 5.5 3.0 to 3.6 3.4 1.4 7.2 5.0 3.0 to 3.6 1.4 8.3 4.5 to 5.5 6.9 15.8 2.2 to 3.0 0.2 0.6 3.0 to 3.6 0.3 0.7 4.5 to 5.5 3.0 to 3.6 2.5 to 3.0 4.5 to 5.5 3.0 to 3.6 2.2 to 3.0 4.5 to 5.5 5.5 2.8 2.3 3.0 1.5 1.2 0.6 12.6 7.1 5.7 7.2 3.8 3.0 1.5 3.0 to 3.6 4.1 9.8 4.5 to 5.5 8.0 17.2 min Specification typ max unit
mA
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors.
Continued on next page.
No.A0965-19/25
LC877696B/80B/64B/48B
Continued from preceding page.
Parameter HALT mode consumption current (Note 7-1) IDDHALT(2) Symbol IDDHALT(1) Pin/ Remarks VDD1 =VDD2 =VDD3 HALT mode * FmCF=12MHz ceramic oscillation * FmX'tal=32.768kHz crystal oscillation mode * System clock set to 12MHz side. * Internal RC oscillation stopped * Multifrequency RC oscillation stopped * 1/1 frequency division ratio IDDHALT(3) HALT mode * FmCF=8MHz ceramic oscillation mode IDDHALT(4) * FmX'tal=32.768kHz crystal oscillation mode * System clock set to 8MHz side * Internal RC oscillation stopped IDDHALT(5) * Multifrequency RC oscillation stopped * 1/1 frequency division ratio IDDHALT(6) HALT mode * FmCF=4MHz ceramic oscillation mode IDDHALT(7) * FmX'tal=32.768kHz crystal oscillation mode * System clock set to 4MHz side IDDHALT(8) * Internal RC oscillation stopped * Multifrequency RC oscillation stopped * 1/2 frequency division ratio IDDHALT(9) IDDHALT(10) IDDHALT(11) IDDHALT(12) HALT mode * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz crystal oscillation mode * System clock set to internal RC oscillation * Multifrequency RC oscillation stopped * 1/2 frequency division ratio HALT mode * FmCF=0Hz (oscillation stopped) * FmX'tal=32.768kHz crystal oscillation mode IDDHALT(13) * Internal RC oscillation stopped * System clock set to 10MHz multifrequency RC oscillation * 1/1 frequency division ratio IDDHALT(14) HALT mode * FmCF=0Hz (oscillation stopped) IDDHALT(15) * FmX'tal=32.768kHz crystal oscillation mode * Internal RC oscillation stopped * System clock set to 4MHz multifrequency RC IDDHALT(16) oscillation * 1/1 frequency division ratio IDDHALT(17) HALT mode * FmCF=0Hz (oscillation stopped) IDDHALT(18) * FmX'tal=32.768kHz crystal oscillation mode * System clock set to 32.768kHz side * Internal RC oscillation stopped IDDHALT(19) * Multifrequency RC oscillation stopped * 1/2 frequency division ratio HOLD mode consumption current Clock HOLD mode consumption current IDDHOLD(6) IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) IDDHOLD(4) IDDHOLD(5) VDD1 VDD1 HOLD mode * CF1=VDD or open (external clock mode) Clock HOLD mode * CF1=VDD or open (external clock mode) * FmX'tal=32.768kHz crystal oscillation mode 4.5 to 5.5 3.0 to 3.6 1.7 to 3.0 4.5 to 5.5 3.0 to 3.6 1.7 to 3.0 0.14 0.03 0.03 17.5 3.8 2.4 35 28 26 125.3 60 50 1.7 to 3.0 3.5 57.9 A 3.0 to 3.6 5.1 67.1 4.5 to 5.5 20.2 114.6 2.2 to 3.0 0.5 1.2 3.0 to 3.6 0.6 1.5 4.5 to 5.5 1.3 3.1 3.0 to 3.6 1.2 3.1 4.5 to 5.5 2.6 6.0 2.2 to 3.0 0.10 0.3 4.5 to 5.5 3.0 to 3.6 0.3 0.13 0.8 0.4 2.2 to 3.0 0.4 1.1 mA 3.0 to 3.6 0.5 1.5 4.5 to 5.5 1.2 3.3 2.5 to 3.0 0.7 5.7 3.0 to 3.6 0.9 7.1 4.5 to 5.5 2.0 12.6 3.0 to 3.6 1.2 3.2 4.5 to 5.5 2.7 6.2 Conditions VDD[V] min Specification typ max unit
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up resistors.
No.A0965-20/25
LC877696B/80B/64B/48B
UART (Full Duplex) Operating Conditions at Ta = -20 to +70C, VSS1 = VSS2 = VSS3 = 0V
Parameter Transfer rate Symbol UBR Pin/Remarks UTX(P00), URX(P01) Conditions VDD[V] 2.2 to 5.5 min 16/3 Specification typ max 8192/3 unit tCYC
Data length: 7/8/9 bits (LSB first) Stop bits: 1 bit (2-bit in continuous data transmission mode) Parity bits: None Example of 8-bit Data Transmission Mode Processing (Transmit Data=55H)
Start bit Start of transmission Transmit data (LSB first) Stop bit End of transmission
UBR
Example of 8-bit Data Reception Mode Processing (Receive Data=55H)
Stop bit Receive data (LSB first) End of reception
Start bit Start of reception
UBR
* When using UART, set P0LDDR (P0DDR: BIT0) to "0"
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a SANYO-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal Frequency Vendor Name Circuit Constant Oscillator Name C1 [pF] 12MHz MURATA CSTCE120G52-R0 CSTLS8M00G53-B0 CSTCE8M00G52-R0 4MHz MURATA CSTLS4M00G53-B0 CSTCR4M00G53-R0 (10) (15) (10) (15) (15) C2 [pF] (10) (15) (10) (15) (15) Rf1 [] OPEN OPEN OPEN OPEN OPEN Rd1 [] 330 680 330 1.5k 1k Operating Voltage Range [V] 3.0 to 5.5 2.5 to 5.5 2.5 to 5.5 2.2 to 5.5 2.5 to 5.5 Oscillation Stabilization Time typ [ms] 0.05 0.05 0.05 0.05 0.05 max [ms] 0.15 0.15 0.15 0.15 0.15 Built-in C1, C2 Built-in C1, C2 Built-in C1, C2 Remarks
8MHz
MURATA
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD goes above the operating voltage lower limit (see Figure 4).
No.A0965-21/25
LC877696B/80B/64B/48B
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a SANYOdesignated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal Frequency 32.768kHz Vendor Name Oscillator Name C3 [pF] Circuit Constant C4 [pF] Rf2 [] Rd2 [] Operating Voltage Range [V] Oscillation Stabilization Time typ [s] max [s] Remarks
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the oscillation to get stabilized after the HOLD mode is reset (see Figure 4). Caution: The components that are involved in oscillation should be placed as close to the IC and to one another as possible because they are vulnerable to the influences of the circuit pattern.
CF1
CF2
XT1
XT2
Rf1
Rd1
Rf2
Rd2
C1 CF
C2
C3 X'tal
C4
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A0965-22/25
LC877696B/80B/64B/48B
Power supply
VDD Operating VDD lower limit 0V Reset time
RES
Internal RC oscillation tmsCF CF1, CF2
tmsX'tal XT1, XT2
Operating mode
Unpredictable
Reset
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset signal
HOLD reset signal absent
HOLD release signal VALID
Internal RC oscillation tmsCF CF1, CF2
tmsX'tal XT1, XT2
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time Figure 4 Oscillation Stabilization Times
No.A0965-23/25
LC877696B/80B/64B/48B
VDD
RRES
RES CRES
Note: Determine the value of CRES and RRES so that the reset signal is present for a period of 200s after the supply voltage goes beyond the lower limit of the IC's operating voltage.
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7 Data RAM transfer period (SIO0 only)
DO8
tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: Data RAM transfer period (SIO0 only) tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA thDI tSCKH
Figure 6 Serial I/O Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A0965-24/25
LC877696B/80B/64B/48B
VDD SW : ON/OFF (programmable)
RLCD RLCD RLCD RLCD VLCD RLCD RLCD 2/3VLCD RLCD 1/2VLCD RLCD 1/3VLCD RLCD RLCD GND SW: ON when VLCD=VDD
Figure 8 LCD Bias Resistors
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of September, 2007. Specifications and information herein are subject to change without notice.
PS No.A0965-25/25

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